In a semiconductor device, absolute maximum rating of a power supply voltage is set. When a voltage exceeding this absolute maximum rating is applied to the semiconductor device, the semiconductor device may be broken down. As such a case where the voltage exceeding the absolute maximum rating is applied to the semiconductor device, an ESD (Electro Static Discharge) that enters the semiconductor device from an outside of the semiconductor device may be pointed out.
Patent Literature 1 discloses a technique of employing a GGNMOS (Gate Grounded NMOS) transistor where a gate, a source, and a substrate potential of an N-channel type MOS transistor are connected to a ground potential, as an ESD) protection circuit.
Further, Patent Literature 2 discloses a technique of employing a diode element connected between terminals of different power supply systems as an ESD protection circuit, in a semiconductor device including the different power supply systems.
[Patent Literature 1]
    JP Patent Kokai Publication No. JP-2004-304136A, which corresponds to US2004/195625A1[Patent Literature 2]    JP Patent Kokai Publication No. JP-2010-205871A